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All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.
全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。
Chip timing synchronization between local spread sequence and transmitted spread sequence is critical. in DS-CDMA receiver.
在DS - CD MA接收机中，正确解调的首要条件是实现本地扩频码与发送扩频码的码片同步。
To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured.
为了克服制程、电压、温度变异所造成的影响，自动时脉偏移同步方案可以在晶片制造出来之后动态地调整并降低时脉偏移。
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